Ferrite · compiler and hardware research

Correctness needs an independent witness.

An embedded hardware DSL, cycle simulator, and RTL generator in Rust. A circuit is explicit; its behavior must survive another implementation.

Engineering maturity: A1–A3 implemented in the inspected revision
Research registry: Unregistered
Lithic revision: b9c0986
Source inspected: 2026-10-06

Sourceinput
Graph · Strataimplemented
Schedule · HLSresearch
RTL · Lithicimplemented
Gates · synthesisresearch
Placementresearch
Routingresearch
Dieresearch

The third layer of Ferrite: an explicit circuit, checked more than one way.

Future scope

A1–A3 implemented in the inspected revision. Hardware source and tests exist. Algorithm-to-circuit HLS, physical implementation, signoff, and foundry-qualified silicon remain future scope.

Lithic on GitHub Design and limitation record Repository documentation site

Fig. 3 · Independent witnesses

One circuit representation. Independent execution paths. Software references, cycle simulation, and Verilator test different failure surfaces. Agreement on finite stimuli is not physical signoff.

Implemented tooling and limits

Revision b9c0986

Implemented circuit tooling Available

Runtime-width bitvectors and arena-based signal IR
Embedded Rust hardware DSL
Cycle simulator and deterministic Verilog emitter
Port derivation, cycle-indexed waveforms, and VCD
Step testbenches and Verilator cosimulation

Boundaries that matter Limitations

No initialized-memory IR node; ROM tables become mux/case trees
The simulator refuses multiple clocks and unmodelled instances
BLAKE3 and FFT source files are placeholders, not implemented corpus modules
RTL equivalence is not physical signoff or proof of a tapeout

A witness you can clock

Re-derived in your browser · not Lithic output

The smallest streaming design in the corpus, as its source builds it: three flops, eight XOR stages, one byte per cycle. Run a message through it, then flip the tap to the mistake the corpus documents and watch a perfectly plausible circuit compute the wrong answer.

Clock cycle0 / 9

Against software CRCCRC 0x2 · reference 0x2 · match

Message (ASCII)

Each clock edge consumes one byte. Inside the cycle the byte's eight bits pass through eight XOR stages, least significant first: feedback = s₀ ⊕ bit, shift right, and where feedback is 1 the tap flips s₂ and s₁. Three flops hold the result.

Fig. Witness · Lithic corpus design CRC-3/ROTD

Width 3, polynomial 0x3, init 0, reflected input and output, check value 0x2 for "123456789". The design and its tap come from ferrite-lithic-corpus/src/crc3.rs at the pinned Lithic revision; the corpus notes that a tap of 0b011 "is still a three-bit LFSR … just computing a different CRC". This page re-derives the datapath in JavaScript and checks it against an independent textbook CRC. It is not Lithic simulation, generated Verilog, a Verilator run or a measurement.

Cycle table for "123456789"

Cycle	Byte in	Register after (s₂s₁s₀)
1	'1' · 0x31	100
2	'2' · 0x32	001
3	'3' · 0x33	011
4	'4' · 0x34	111
5	'5' · 0x35	011
6	'6' · 0x36	110
7	'7' · 0x37	100
8	'8' · 0x38	100
9	'9' · 0x39	010

Execution paths and corpus

From repository source and CI

One graph. Two execution paths.

manual hardware description
            ↓
        signal graph
       ↙            ↘
cycle simulator    RTL emitter
       │              ↓
       │           Verilog
       │              ↓
       │          Verilator
       └──── compare ─┘
              ↑
      software reference

The simulator records before/after-edge observations and commits state with explicit clock semantics. The emitter constructs deterministic Verilog. Independent software references and Verilator test different failure surfaces; neither simulation alone nor finite-stimulus agreement establishes physical correctness.

Nine tool crates and the corpus.

ferrite-lithic-bits
ferrite-lithic-ir
ferrite-lithic
ferrite-lithic-sim
ferrite-lithic-rtl
ferrite-lithic-derive
ferrite-lithic-wave
ferrite-lithic-cosim
ferrite-lithic-tb
ferrite-lithic-corpus

Real designs find different defects.

The inspected repository reports 21 designs across seven tiers. The corpus includes:

CRC-3 and CRC-32
AES-128, ChaCha20, SHA-256, GHASH
Bitpacking, hex, Base64, RLE, sorting, Roaring bitmap
DFA, Aho–Corasick, memchr, packet parsing
Bloom/CMS/FNV sketches, Huffman, FSE, and DEFLATE

BLAKE3 and FFT are unimplemented files, not implemented corpus modules. Future ML kernels and complete systems described in Source-to-Silicon are proposed additions. Aggregate test totals are omitted because repository summaries contain inconsistent breakdowns.

A skipped equivalence test proves nothing.

Local Rust tests can run without Verilator or Icarus and print skips. The dedicated cosimulation CI job installs both external tools and fails if any gated test skips. The website describes that test architecture; it does not claim to have rerun the Rust corpus or certify a tapeout.

Inspect the cosimulation CI contract ↗

Memory is not a hidden promise.

Zero-filled memories exist. Initialized memory is absent from the IR, and ROM lookup tables lower to mux/case trees. This can differ substantially from the memory macro a physical design needs. A future HLS and process layer must preserve initialization, ports, latency, timing, and implementation cost explicitly.

From circuit tooling to the silicon research horizon Previous implemented layer: Strata

Implementation record

Inspected 2026-10-06

Current capabilities describe repository source inspected on 2026-10-06. Repository test reports are attributed to their authors; this publication does not independently certify a hardware flow.

Strata at e1da679 Lithic at b9c0986 Ostrium evidence record