Ferrite · compiler and hardware research
From computation to physical silicon.
Algorithms become architectures. Architectures become circuits. Circuits become layouts. Layouts become silicon.
- Sourceinput
- Graph · Strataimplemented
- Schedule · HLSresearch
- RTL · Lithicimplemented
- Gates · synthesisresearch
- Placementresearch
- Routingresearch
- Dieresearch
Experimental engineering foundations / unregistered source-to-silicon research. The complete stack is a long-term objective, not an available toolchain.
- 01 Strata Model graph → executable partitions Implemented core
- 02 HLS Algorithm → microarchitecture Research roadmap
- 03 Lithic Hardware description → signal graph → Verilog Implemented core
- 04 Synthesis RTL → standard-cell netlist Research roadmap
- 05 Physical Gates → placed and routed layout Research roadmap
- 06 Signoff Layout → independently checked design database Research roadmap
- 07 Silicon Accepted database → manufactured and tested device Ultimate objective
The Ferrite compiler research stack
Strata and Lithic are implemented foundations. HLS, synthesis, physical implementation, and signoff are research layers. Foundry handoff and silicon remain an ultimate objective. Dashed connections do not represent an implemented end-to-end compiler.
Solid rules mark implemented foundations; dashed rules mark research and manufacturing gates. The chain is a research architecture, not an available end-to-end flow.
The descent · source to silicon
Computation becomes matter.
- 01
Strata
implemented
What should become hardware?
Model graph → executable partitions
Graph IR, partitioning, CPU reference, and host execution exist. GPU execution and automatic ASIC generation do not.
- 02
HLS
research
What architecture should the algorithm become?
Algorithm → microarchitecture
No HLS implementation is present in the inspected repositories.
- 03
Lithic
implemented
What exact circuit implements the architecture?
Hardware description → signal graph → Verilog
Embedded DSL, simulator, emitter, waveforms, and cosimulation exist. An algorithm-to-circuit HLS front end is future work.
- 04
Synthesis
research
Which gates implement the circuit?
RTL → standard-cell netlist
Ferrite-owned Boolean optimization and technology mapping are proposed.
- 05
Physical
research
How does the circuit become geometry?
Gates → placed and routed layout
The placement and routing demonstrations on this site are educational schematics, not Ferrite output.
- 06
Signoff
research
Does the implementation meet the process contract?
Layout → independently checked design database
No Ferrite foundry-qualified timing, physical verification, or signoff stack is demonstrated.
- 07
Silicon
north star
Will the physical result survive fabrication?
Accepted database → manufactured and tested device
Authorized process access, tool qualification, fabrication, packaging, and test are separate gates. No N3 support or tapeout is claimed.
A compiler research programme
Two foundations · five research gatesA coherent compiler research programme.
Ferrite connects Strata's system-level graph boundary with Lithic's explicit circuits. Source-to-Silicon extends that inquiry toward HLS, logic synthesis, physical implementation, and semiconductor verification inside an open Rust-native architecture.
What should become hardware? Which architecture should it become? What circuit implements it? And what does the fabrication process permit?
Compiler architecture
Expand a layer · solid = implemented · dashed = researchOne question. Many boundaries.
The path is a research architecture, not an implemented end-to-end flow. Strata can route computation to software backends; the custom-hardware branch would enter HLS.
Solid rules identify existing foundations. Dashed rules mark research and manufacturing gates.
-
01 Ferrite StrataModel graph → executable partitions Implemented core
What should become hardware?
- Query backend support before compilation
- Partition graphs at the subgraph boundary
- Run CPU reference kernels and unsupported nodes on the host
- Future: select economically justified custom hardware
BoundaryRead the Ferrite Strata recordGraph IR, partitioning, CPU reference, and host execution exist. GPU execution and automatic ASIC generation do not.
-
02 Ferrite HLSAlgorithm → microarchitecture Research roadmap
What architecture should the algorithm become?
- Dependence analysis and modulo scheduling
- Resource allocation, sharing, and binding
- Loop unrolling and pipeline construction
- Memory banking, bit widths, and control synthesis
BoundaryNo HLS implementation is present in the inspected repositories.
-
03 Ferrite LithicHardware description → signal graph → Verilog Implemented core
What exact circuit implements the architecture?
- Represent fixed-width signals and circuit dependencies
- Simulate explicit cycle semantics
- Emit deterministic Verilog
- Compare software models, simulation, and emitted RTL
BoundaryRead the Ferrite Lithic recordEmbedded DSL, simulator, emitter, waveforms, and cosimulation exist. An algorithm-to-circuit HLS front end is future work.
-
04 Ferrite SynthesisRTL → standard-cell netlist Research roadmap
Which gates implement the circuit?
- Register-transfer and Boolean representations
- Constant propagation and dead-logic elimination
- Mux, FSM, arithmetic, and register optimization
- Retiming, clock gating, and technology mapping
BoundaryFerrite-owned Boolean optimization and technology mapping are proposed.
-
05 Ferrite PhysicalGates → placed and routed layout Research roadmap
How does the circuit become geometry?
- Floorplan and legalize standard cells and macros
- Construct clocks and power distribution
- Global routing, track assignment, detailed routing
- Extract parasitics and return physical feedback
BoundaryThe placement and routing demonstrations on this site are educational schematics, not Ferrite output.
-
06 Ferrite SignoffLayout → independently checked design database Research roadmap
Does the implementation meet the process contract?
- Static timing, power, IR drop, and electromigration
- RC extraction, DRC, LVS, and antenna checking
- Density, metal fill, and reliability checks
- Correlation with independent and foundry-approved references
BoundaryNo Ferrite foundry-qualified timing, physical verification, or signoff stack is demonstrated.
-
07 Foundry handoff → siliconAccepted database → manufactured and tested device Ultimate objective
Will the physical result survive fabrication?
- Authorized process and library data
- Foundry acceptance and reference-flow correlation
- Test vehicle, fabrication, and measured silicon
- Long-term target: advanced-node FinFET manufacturing
BoundaryAuthorized process access, tool qualification, fabrication, packaging, and test are separate gates. No N3 support or tapeout is claimed.
Current and future maturity
Engineering maturity · not research evidenceImplemented today
Strata: Graph IR and backend/executable traits; Backend capability queries and graph partitioning; CPU reference kernels; Session, compile, run, and host fallback.
Lithic: Runtime-width bitvectors and arena-based signal IR; Embedded Rust hardware DSL; Cycle simulator and deterministic Verilog emitter; Port derivation, cycle-indexed waveforms, and VCD; Step testbenches and Verilator cosimulation.
In development
Strata's B1 core remains the active development scope. Current source has three crates; the broader backend/plugin/PyTorch design is not fully implemented.
Research roadmap
Algorithm-to-architecture HLS, Ferrite-owned synthesis, process contracts, characterization, physical implementation, and independent signoff correlation.
Ultimate objective
A foundry-manufacturable result from a complete Rust-native source-to-silicon flow using authorized process data. Advanced-node tapeout is an external evidence gate.
Implementation record
Inspected 2026-10-06Current capabilities describe repository source inspected on 2026-10-06. Repository test reports are attributed to their authors; this publication does not independently certify a hardware flow.