Loop Compression
Single Researcher Problem-to-Validation Latency
HYPOTHESIS
For a defined and reproducible capability class, systematic improvements to the Ostrium research loop—better AI-assisted hypothesis generation, faster experimentation, tighter falsification cycles—reduce the median wall-clock time from problem specification to experimentally validated capability.
The foundational empirical rung. Directly tests whether research loop tooling can compress the time required to solve novel problems and validate working capability.
KILL CONDITION
Multiple experiments across independently selected capability classes show no measurable time reduction despite loop improvements, or bottleneck analysis reveals binding constraints outside the loop.
- Falsification metric
- Median wall-clock latency (tau_loop) delta vs matched baseline
PROTOCOL
- Scope
- Single research loop (problem specification → hypothesis → experiment → validation)
- Latency nodes
- information, reasoning, scientific, engineering
- Counterfactual baseline
- Execution by matched human engineering baseline without autonomous loop tools.
- Success condition
- Statistically significant (p < 0.05, effect size d > 0.5) reduction in wall-clock time across independently selected capability classes.
EVIDENCE
No replicated experimental results recorded for this program.
Source: RESEARCH.md v1.0. Read the governing doctrine →